/* linux/include/asm-arm/arch-at91sam9260/at91sam9260_matrix.h
 * 
 * Hardware definition for the matrix peripheral in the ATMEL at91sam9260 processor
 * 
 * Generated  12/07/2006 (15:04:00) AT91 SW Application Group from HMATRIX1_SAM9260 V1.5
 * 
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 * 
 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 * 
 * You should have received a copy of the  GNU General Public License along
 * with this program; if not, write  to the Free Software Foundation, Inc.,
 * 675 Mass Ave, Cambridge, MA 02139, USA.
 */


#ifndef __AT91SAM9260_MATRIX_H
#define __AT91SAM9260_MATRIX_H

/* -------------------------------------------------------- */
/* MATRIX ID definitions for  AT91SAM9260           */
/* -------------------------------------------------------- */

/* -------------------------------------------------------- */
/* MATRIX Base Address definitions for  AT91SAM9260   */
/* -------------------------------------------------------- */
#define AT91C_BASE_MATRIX    	0xFFFFEE00 /**< MATRIX base address */

/* -------------------------------------------------------- */
/* PIO definition for MATRIX hardware peripheral */
/* -------------------------------------------------------- */

/* -------------------------------------------------------- */
/* Register offset definition for MATRIX hardware peripheral */
/* -------------------------------------------------------- */
#define MATRIX_MCFG0 	(0x0000) 	/**<  Master Configuration Register 0 (ram96k)      */
#define MATRIX_MCFG1 	(0x0004) 	/**<  Master Configuration Register 1 (rom)     */
#define MATRIX_MCFG2 	(0x0008) 	/**<  Master Configuration Register 2 (hperiphs)  */
#define MATRIX_MCFG3 	(0x000C) 	/**<  Master Configuration Register 3 (ebi) */
#define MATRIX_MCFG4 	(0x0010) 	/**<  Master Configuration Register 4 (bridge)     */
#define MATRIX_MCFG5 	(0x0014) 	/**<  Master Configuration Register 5 (mailbox)     */
#define MATRIX_MCFG6 	(0x0018) 	/**<  Master Configuration Register 6 (ram16k)   */
#define MATRIX_MCFG7 	(0x001C) 	/**<  Master Configuration Register 7 (teak_prog)      */
#define MATRIX_SCFG0 	(0x0040) 	/**<  Slave Configuration Register 0 (ram96k)      */
#define MATRIX_SCFG1 	(0x0044) 	/**<  Slave Configuration Register 1 (rom)     */
#define MATRIX_SCFG2 	(0x0048) 	/**<  Slave Configuration Register 2 (hperiphs)  */
#define MATRIX_SCFG3 	(0x004C) 	/**<  Slave Configuration Register 3 (ebi) */
#define MATRIX_SCFG4 	(0x0050) 	/**<  Slave Configuration Register 4 (bridge)     */
#define MATRIX_PRAS0 	(0x0080) 	/**<  PRAS0 (ram0)  */
#define MATRIX_PRBS0 	(0x0084) 	/**<  PRBS0 (ram0)  */
#define MATRIX_PRAS1 	(0x0088) 	/**<  PRAS1 (ram1)  */
#define MATRIX_PRBS1 	(0x008C) 	/**<  PRBS1 (ram1)  */
#define MATRIX_PRAS2 	(0x0090) 	/**<  PRAS2 (ram2)  */
#define MATRIX_PRBS2 	(0x0094) 	/**<  PRBS2 (ram2)  */
#define MATRIX_MRCR 	(0x0100) 	/**<  Master Remp Control Register  */
#define MATRIX_EBI 	(0x011C) 	/**<  Slave 3 (ebi) Special Function Register */
#define MATRIX_TEAKCFG 	(0x012C) 	/**<  Slave 7 (teak_prog) Special Function Register */
#define MATRIX_VERSION 	(0x01FC) 	/**<  Version Register */

/* -------------------------------------------------------- */
/* Bitfields definition for MATRIX hardware peripheral */
/* -------------------------------------------------------- */
/* --- Register MATRIX_SCFG0 */
#define AT91C_MATRIX_SLOT_CYCLE (0xFF << 0 ) /**< (MATRIX) Maximum Number of Allowed Cycles for a Burst */
#define AT91C_MATRIX_DEFMSTR_TYPE (0x3 << 16) /**< (MATRIX) Default Master Type */
#define 	AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR           (0x0 << 16) /**< (MATRIX) No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This results in having a one cycle latency for the first transfer of a burst. */
#define 	AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR         (0x1 << 16) /**< (MATRIX) Last Default Master. At the end of current slave access, if no other master request is pending, the slave stay connected with the last master having accessed it. This results in not having the one cycle latency when the last master re-trying access on the slave. */
#define 	AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR        (0x2 << 16) /**< (MATRIX) Fixed Default Master. At the end of current slave access, if no other master request is pending, the slave connects with fixed which number is in FIXED_DEFMSTR field. This results in not having the one cycle latency when the fixed master re-trying access on the slave. */
#define AT91C_MATRIX_FIXED_DEFMSTR0 (0x7 << 18) /**< (MATRIX) Fixed Index of Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR0_ARM926I              (0x0 << 18) /**< (MATRIX) ARM926EJ-S Instruction Master is Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR0_ARM926D              (0x1 << 18) /**< (MATRIX) ARM926EJ-S Data Master is Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR0_HPDC3                (0x2 << 18) /**< (MATRIX) HPDC3 Master is Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR0_LCDC                 (0x3 << 18) /**< (MATRIX) LCDC Master is Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR0_DMA                  (0x4 << 18) /**< (MATRIX) DMA Master is Default Master */
/* --- Register MATRIX_SCFG1 */
#define AT91C_MATRIX_SLOT_CYCLE (0xFF << 0 ) /**< (MATRIX) Maximum Number of Allowed Cycles for a Burst */
#define AT91C_MATRIX_DEFMSTR_TYPE (0x3 << 16) /**< (MATRIX) Default Master Type */
#define 	AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR           (0x0 << 16) /**< (MATRIX) No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This results in having a one cycle latency for the first transfer of a burst. */
#define 	AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR         (0x1 << 16) /**< (MATRIX) Last Default Master. At the end of current slave access, if no other master request is pending, the slave stay connected with the last master having accessed it. This results in not having the one cycle latency when the last master re-trying access on the slave. */
#define 	AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR        (0x2 << 16) /**< (MATRIX) Fixed Default Master. At the end of current slave access, if no other master request is pending, the slave connects with fixed which number is in FIXED_DEFMSTR field. This results in not having the one cycle latency when the fixed master re-trying access on the slave. */
#define AT91C_MATRIX_FIXED_DEFMSTR1 (0x7 << 18) /**< (MATRIX) Fixed Index of Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR1_ARM926I              (0x0 << 18) /**< (MATRIX) ARM926EJ-S Instruction Master is Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR1_ARM926D              (0x1 << 18) /**< (MATRIX) ARM926EJ-S Data Master is Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR1_HPDC3                (0x2 << 18) /**< (MATRIX) HPDC3 Master is Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR1_LCDC                 (0x3 << 18) /**< (MATRIX) LCDC Master is Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR1_DMA                  (0x4 << 18) /**< (MATRIX) DMA Master is Default Master */
/* --- Register MATRIX_SCFG2 */
#define AT91C_MATRIX_SLOT_CYCLE (0xFF << 0 ) /**< (MATRIX) Maximum Number of Allowed Cycles for a Burst */
#define AT91C_MATRIX_DEFMSTR_TYPE (0x3 << 16) /**< (MATRIX) Default Master Type */
#define 	AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR           (0x0 << 16) /**< (MATRIX) No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This results in having a one cycle latency for the first transfer of a burst. */
#define 	AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR         (0x1 << 16) /**< (MATRIX) Last Default Master. At the end of current slave access, if no other master request is pending, the slave stay connected with the last master having accessed it. This results in not having the one cycle latency when the last master re-trying access on the slave. */
#define 	AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR        (0x2 << 16) /**< (MATRIX) Fixed Default Master. At the end of current slave access, if no other master request is pending, the slave connects with fixed which number is in FIXED_DEFMSTR field. This results in not having the one cycle latency when the fixed master re-trying access on the slave. */
#define AT91C_MATRIX_FIXED_DEFMSTR2 (0x1 << 18) /**< (MATRIX) Fixed Index of Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR2_ARM926I              (0x0 << 18) /**< (MATRIX) ARM926EJ-S Instruction Master is Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR2_ARM926D              (0x1 << 18) /**< (MATRIX) ARM926EJ-S Data Master is Default Master */
/* --- Register MATRIX_SCFG3 */
#define AT91C_MATRIX_SLOT_CYCLE (0xFF << 0 ) /**< (MATRIX) Maximum Number of Allowed Cycles for a Burst */
#define AT91C_MATRIX_DEFMSTR_TYPE (0x3 << 16) /**< (MATRIX) Default Master Type */
#define 	AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR           (0x0 << 16) /**< (MATRIX) No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This results in having a one cycle latency for the first transfer of a burst. */
#define 	AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR         (0x1 << 16) /**< (MATRIX) Last Default Master. At the end of current slave access, if no other master request is pending, the slave stay connected with the last master having accessed it. This results in not having the one cycle latency when the last master re-trying access on the slave. */
#define 	AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR        (0x2 << 16) /**< (MATRIX) Fixed Default Master. At the end of current slave access, if no other master request is pending, the slave connects with fixed which number is in FIXED_DEFMSTR field. This results in not having the one cycle latency when the fixed master re-trying access on the slave. */
#define AT91C_MATRIX_FIXED_DEFMSTR3 (0x7 << 18) /**< (MATRIX) Fixed Index of Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR3_ARM926I              (0x0 << 18) /**< (MATRIX) ARM926EJ-S Instruction Master is Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR3_ARM926D              (0x1 << 18) /**< (MATRIX) ARM926EJ-S Data Master is Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR3_HPDC3                (0x2 << 18) /**< (MATRIX) HPDC3 Master is Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR3_LCDC                 (0x3 << 18) /**< (MATRIX) LCDC Master is Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR3_DMA                  (0x4 << 18) /**< (MATRIX) DMA Master is Default Master */
/* --- Register MATRIX_SCFG4 */
#define AT91C_MATRIX_SLOT_CYCLE (0xFF << 0 ) /**< (MATRIX) Maximum Number of Allowed Cycles for a Burst */
#define AT91C_MATRIX_DEFMSTR_TYPE (0x3 << 16) /**< (MATRIX) Default Master Type */
#define 	AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR           (0x0 << 16) /**< (MATRIX) No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This results in having a one cycle latency for the first transfer of a burst. */
#define 	AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR         (0x1 << 16) /**< (MATRIX) Last Default Master. At the end of current slave access, if no other master request is pending, the slave stay connected with the last master having accessed it. This results in not having the one cycle latency when the last master re-trying access on the slave. */
#define 	AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR        (0x2 << 16) /**< (MATRIX) Fixed Default Master. At the end of current slave access, if no other master request is pending, the slave connects with fixed which number is in FIXED_DEFMSTR field. This results in not having the one cycle latency when the fixed master re-trying access on the slave. */
#define AT91C_MATRIX_FIXED_DEFMSTR4 (0x3 << 18) /**< (MATRIX) Fixed Index of Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR4_ARM926I              (0x0 << 18) /**< (MATRIX) ARM926EJ-S Instruction Master is Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR4_ARM926D              (0x1 << 18) /**< (MATRIX) ARM926EJ-S Data Master is Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR4_HPDC3                (0x2 << 18) /**< (MATRIX) HPDC3 Master is Default Master */
/* --- Register MATRIX_MRCR */
#define AT91C_MATRIX_RCA926I  (0x1 << 0 ) /**< (MATRIX) Remap Command for ARM926EJ-S Instruction Master */
#define AT91C_MATRIX_RCA926D  (0x1 << 1 ) /**< (MATRIX) Remap Command for ARM926EJ-S Data Master */
/* --- Register MATRIX_EBI */
#define AT91C_MATRIX_CS1A     (0x1 << 1 ) /**< (MATRIX) Chip Select 1 Assignment */
#define 	AT91C_MATRIX_CS1A_SMC                  (0x0 <<  1) /**< (MATRIX) Chip Select 1 is assigned to the Static Memory Controller. */
#define 	AT91C_MATRIX_CS1A_SDRAMC               (0x1 <<  1) /**< (MATRIX) Chip Select 1 is assigned to the SDRAM Controller. */
#define AT91C_MATRIX_CS3A     (0x1 << 3 ) /**< (MATRIX) Chip Select 3 Assignment */
#define 	AT91C_MATRIX_CS3A_SMC                  (0x0 <<  3) /**< (MATRIX) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC. */
#define 	AT91C_MATRIX_CS3A_SM                   (0x1 <<  3) /**< (MATRIX) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated. */
#define AT91C_MATRIX_CS4A     (0x1 << 4 ) /**< (MATRIX) Chip Select 4 Assignment */
#define 	AT91C_MATRIX_CS4A_SMC                  (0x0 <<  4) /**< (MATRIX) Chip Select 4 is only assigned to the Static Memory Controller and NCS4 behaves as defined by the SMC. */
#define 	AT91C_MATRIX_CS4A_CF                   (0x1 <<  4) /**< (MATRIX) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic (first slot) is activated. */
#define AT91C_MATRIX_CS5A     (0x1 << 5 ) /**< (MATRIX) Chip Select 5 Assignment */
#define 	AT91C_MATRIX_CS5A_SMC                  (0x0 <<  5) /**< (MATRIX) Chip Select 5 is only assigned to the Static Memory Controller and NCS5 behaves as defined by the SMC */
#define 	AT91C_MATRIX_CS5A_CF                   (0x1 <<  5) /**< (MATRIX) Chip Select 5 is assigned to the Static Memory Controller and the CompactFlash Logic (second slot) is activated. */
#define AT91C_MATRIX_DBPUC    (0x1 << 8 ) /**< (MATRIX) Data Bus Pull-up Configuration */
/* --- Register MATRIX_TEAKCFG */
#define AT91C_TEAK_PROGRAM_ACCESS (0x1 << 0 ) /**< (MATRIX) TEAK program memory access from AHB */
#define 	AT91C_TEAK_PROGRAM_ACCESS_DISABLED             0x0 /**< (MATRIX) TEAK program access disabled */
#define 	AT91C_TEAK_PROGRAM_ACCESS_ENABLED              0x1 /**< (MATRIX) TEAK program access enabled */
#define AT91C_TEAK_BOOT       (0x1 << 1 ) /**< (MATRIX) TEAK program start from boot routine */
#define 	AT91C_TEAK_BOOT_DISABLED             (0x0 <<  1) /**< (MATRIX) TEAK program starts from boot routine disabled */
#define 	AT91C_TEAK_BOOT_ENABLED              (0x1 <<  1) /**< (MATRIX) TEAK program starts from boot routine enabled */
#define AT91C_TEAK_NRESET     (0x1 << 2 ) /**< (MATRIX) active low TEAK reset */
#define 	AT91C_TEAK_NRESET_ENABLED              (0x0 <<  2) /**< (MATRIX) active low TEAK reset enabled */
#define 	AT91C_TEAK_NRESET_DISABLED             (0x1 <<  2) /**< (MATRIX) active low TEAK reset disabled */
#define AT91C_TEAK_LVECTORP   (0x3FFFF << 14) /**< (MATRIX) boot routine start address */

#endif /* __AT91SAM9260_MATRIX_H */
